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<iframe src="https://ndatasheet.com/datasheet-frame/300/ZL30256" width="300" height="250" frameborder="0" marginwidth="0" marginheight="0" scrolling="no"></iframe> |
Datasheet Info |
Block Diagram page 7. Register Map section 9.3 Features • One, Two or Three DPLL Channels • Programmable bandwidth, 14Hz to 470Hz • Freerun or h |